Senior FPGA Designer
Exegy
| Company | Exegy |
| Category | Design |
| Location | Montreal |
| Remote | Hybrid |
| Employment | Not stated |
| Level | Senior |
| Salary | Not stated by the employer |
| Posted | 21 Jul 2026 |
| Last verified | 30 Jul 2026 |
| Source | Employer career page (ashby) |
Description
About Exegy
Exegy is a global leader in intelligent market data, advanced trading systems, and future-proof technology. Exegy serves as a trusted partner to the complete ecosystem of the buy-side, sell-side, exchanges, and financial services technology firms around the globe. Headquartered in St. Louis with regional offices in North America, the UK/Europe and Asia Pacific, Exegy has the global footprint to deliver world-class support and managed services to its customer base of elite financial market participants.
Job Summary
Exegy’s FPGA engineering team creates and maintains ultra-low-latency FPGA HDL building blocks and network IP cores used across Exegy products and within the nxFramework Firmware Development Kit (FDK). These components support hardware-accelerated applications for leading financial institutions operating in performance-sensitive trading environments.
The Senior FPGA Designer is a hands-on technical contributor responsible for designing, implementing, verifying, and optimizing complex FPGA solutions. You will work across the full development lifecycle, from requirements and architecture through RTL development, timing closure, board-level validation, test automation, and production support. You will also provide technical guidance to less-experienced engineers and partner with FPGA Architects, software engineers, product teams, and solution teams to deliver maintainable, high-performance designs.
Responsibilities
- Design, develop, and maintain high-performance FPGA logic and reusable HDL building blocks for ultra-low-latency applications
- Translate product and technical requirements into detailed FPGA designs, interfaces, implementation plans, and verification strategies
- Develop and review RTL using VHDL and/or Verilog, with a strong focus on latency, throughput, resource utilization, scalability, and maintainability
- Own significant portions of the FPGA development lifecycle, including simulation, synthesis, place-and-route, timing analysis and closure, hardware bring-up, board-level testing, and release support
- Implement and enhance networking and system protocol components such as TCP, UDP, Ethernet MAC/PCS, PCIe, and DMA at multiple speeds
- Create and maintain automated test environments, unit tests, regression suites, coverage metrics, and hardware validation tools using Python and related technologies
- Diagnose complex design, timing, integration, and performance issues across FPGA, hardware, firmware, and software boundaries
- Conduct peer design and code reviews and help establish consistent engineering practices for quality, documentation, testing, and version control
- Collaborate with FPGA Architects to evaluate design tradeoffs and ensure implementations align with broader platform architecture and long-term product direction
- Mentor FPGA Engineers, share technical knowledge, and contribute to onboarding and development of team members
- Partner with product and solution teams to understand customer and business needs, propose practical technical solutions, and communicate risks, dependencies, and tradeoffs
- Monitor developments in FPGA devices, toolchains, networking technologies, and low-latency design techniques and recommend improvements to the team’s technology and methods
Our Ideal Candidate Has:
- Degree in Electronic Engineering, Electrical Engineering, Computer Engineering, or a related technical discipline
- Typically 5 or more years of professional FPGA design and development experience, including ownership of complex designs through implementation and hardware validation
- Advanced proficiency in VHDL and/or Verilog and the ability to assess RTL for correctness, performance, maintainability, and resource efficiency
- Strong understanding of the complete FPGA development flow, including simulation, synthesis, constraints, static timing analysis, timing closure, place-and-route, and on-board debugging
- Experience developing high-
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