Embedded Software (FW) Engineer
kandou
| Company | kandou |
| Category | Engineering |
| Location | Reading |
| Remote | On-site (inferred) |
| Employment | Not stated |
| Level | Not stated |
| Salary | Not stated by the employer |
| First seen | 24 Jul 2026 (the employer did not state a posting date) |
| Last verified | 7 Aug 2026 |
| Source | Employer ATS (bamboohr) |
Description
At Kandou , we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.
Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient . Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.
Kandou’s architecture is not just an incremental improvement — it’s a foundational shift in how AI hardware is built for the future.
We are actively seeking for an Embedded Software (FW) Engineer
Location: Reading (UK), Lausanne (CH)
Responsibility
• Develop, test and maintain Embedded Software for Kandou AI’s new ASIC products
• Real-time Firmware design on high-speed heterogeneous SoC platform
• Work with Architects and Lead engineers to design and implement according to system and module specifications
• Software design and support for our silicon design infrastructure and workflow
• Participate in and promote current best practices in test, review, integration, automation and delivery of quality software products
Skills
• Working with Heterogeneous multicore systems, including both scalar and vector processors
• Real-world experience of high-speed signalling technologies: PCIe, CXL — particularly link training, equalization and retimer/redriver interaction with host and device PHYs
• Firmware development for Active Electrical Cable (AEC) or retimer/redriver ASICs: cable diagnostics, eye margin monitoring, temperature/voltage telemetry and power-state management
• Memory and network interfacing, virtual memory, simulation and co-simulation
• Firmware Update approaches and algorithms
• Use of simulation and/or FPGAs for pre-silicon development
• Understanding of SerDes technology and PHY register-level tuning
Experience
• 7+ years' experience in designing, coding and debugging real-time applications in C and/or C++ in an embedded environment
• Experience in porting and use of RTOS: Zephyr(preferred), FreeRTOS etc.
• Knowledge of RISC-V CPU architecture; experience writing bare-metal or RTOS-based firmware targeting RISC-V cores (RV32/RV64)
• Board and SoC bring-up with JTAG and other debug mechanisms
• FW Update, bootloaders, secure boot
• Debugging at application, driver and hardware levels
• Interfacing to hardware and peripherals: UART, SPI, I2C/SMBus, I3C
• Commitment to use of modern SW development and test workflow tools (CI / GitLab / Makefile / CMake / TDD etc.)
• Knowledge of management and sideband protocols including SMBus, I3C, MCTP, CMIS